1/9 september 2003 new datasheet according to pcn dsg/ct/2c13 marking:d40nf03l @ std40nf03l n-channel 30v - 0.0090 w - 40a dpak low gate charge stripfet?ii power mosfet n typical r ds (on) = 0.0090 w @ 10 v n typical q g = 22.5 nc @ 5 v n optimal r ds(on) x qg trade-off n conduction losses reduced n switching losses reduced n surface-mounting dpak (to-252) power package in tape & reel (suffix t4") description this application specific power mosfet is the third genaration of stmicroelectronis unique "single feature size?" strip-based process. the resulting transistor shows the best trade-off between on-resistance and gate charge. when used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. this is extremely important for motherboards where fast switching and high efficiency are of paramount importance. applications n specifically designed and optimised for high efficiency cpu core dc/dc converters type v dss r ds(on) i d std40nf03l 30 v <0.011 w 40 a dpak to-252 (suffix t4) 1 3 absolute maximum ratings ( ) current limited by the package ( ) pulse width limited by safe operating area. (1) i sd 40a, di/dt 350a/s, v dd v (br)dss , t j t jmax (2) starting t j = 25 o c, i d = 20a, v dd = 25v symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v dgr drain-gate voltage (r gs = 20 k w ) 30 v v gs gate- source voltage 20 v i d ( ) drain current (continuous) at t c = 25c 40 a i d drain current (continuous) at t c = 100c 28 a i dm ( ) drain current (pulsed) 160 a p tot total dissipation at t c = 25c 80 w derating factor 0.53 w/c dv/dt (1) peak diode recovery voltage slope 5.5 v/ns e as (2) single pulse avalanche energy 850 mj t stg storage temperature -55 to 175 c t j operating junction temperature internal schematic diagram
std40nf03l 2/9 thermal data electrical characteristics (t case = 25 c unless otherwise specified) off on (* ) dynamic rthj-case rthj-amb t l thermal resistance junction-case thermal resistance junction-ambient maximum lead temperature for soldering purpose max max typ 1.88 100 300 c/w c/w c symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125c 1 10 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 100 na symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 a 1v r ds(on) static drain-source on resistance v gs = 10 v i d = 20 a v gs = 5 v i d = 10 a 0.0090 0.0150 0.0110 0.0195 w w symbol parameter test conditions min. typ. max. unit g fs (*) forward transconductance v ds = 15 v i d = 20 a 23 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25v, f = 1 mhz, v gs = 0 1440 560 135 pf pf pf
3/9 std40nf03l switching on switching off source drain diode (*) pulsed: pulse duration = 300 s, duty cycle 1.5 %. ( ) pulse width limited by safe operating area. symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 15 v i d = 20 a r g = 4.7 w v gs = 5 v (resistive load, figure 3) 22 165 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =15 v i d =40 a v gs =5 v 22.5 9 12 30 nc nc nc symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 15 v i d = 20 a r g = 4.7 w, v gs = 5 v (resistive load, figure 3) 21 25 ns ns symbol parameter test conditions min. typ. max. unit i sd i sdm ( ) source-drain current source-drain current (pulsed) 40 160 a a v sd (*) forward on voltage i sd = 20 a v gs = 0 1.3 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 40 a di/dt = 100a/s v dd = 20 v t j = 150c (see test circuit, figure 5) 42 52 2.5 ns nc a electrical characteristics (continued) safe operating area thermal impedance
std40nf03l 4/9 output characteristics transfer characteristics transconductance static drain-source on resistance gate charge vs gate-source voltage capacitance variations
5/9 std40nf03l . . normalized gate threshold voltage vs temperature normalized on resistance vs temperature source-drain diode forward characteristics normalized breakdown voltage vs temperature. . .
std40nf03l 6/9 fig. 1: unclamped inductive load test circuit fig. 1: unclamped inductive load test circuit fig. 2: unclamped inductive waveform fig. 3: switching times test circuits for resistive load fig. 4: gate charge test circuit fig. 5: test circuit for inductive load switching and diode recovery times
7/9 std40nf03l dim. mm inch min. typ. max. min. typ. max. a 2.2 2.4 0.086 0.094 a1 0.9 1.1 0.035 0.043 a2 0.03 0.23 0.001 0.009 b 0.64 0.9 0.025 0.035 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.023 c2 0.48 0.6 0.019 0.023 d 6 6.2 0.236 0.244 e 6.4 6.6 0.252 0.260 g 4.4 4.6 0.173 0.181 h 9.35 10.1 0.368 0.397 l2 0.8 0.031 l4 0.6 1 0.023 0.039 == d l2 l4 1 3 == b e == b2 g 2 a c2 c h a1 detail "a" a2 detail "a" to-252 (dpak) mechanical data 0068772-b
std40nf03l 8/9
9/9 std40nf03l
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